b-18 01/99 2n5020, 2n5021 p-channel silicon junction field-effect transistor analog switches absolute maximum ratings at t a = 25?c reverse gate source & reverse gate drain voltage C 50 v continuous forward gate current 50 ma continuous device power dissipation 500 mw power derating 4 mw/c storage temperature range C 65c to + 200c toe18 package dimensions in inches (mm) pin configuration 1 source 1, 2 gate & case, 3 drain surface mount SMP5020, smp5021 at 25c free air temperature: 2n5020 2n5021 process pj32 static electrical characteristics min max min max unit test conditions gate source breakdown voltage v (br)gdo 25 25 v i g = 1 a, v ds = ?v gate reverse current i gss 11nav gs = 15 v, v ds = ?v gate source cutoff voltage v gs(off) 0.3 1.5 0.5 2.5 v v ds = C 15 v, i d = 1 na drain saturation current (pulsed) i dss C 0.3 C 1.2 C 1 C 3.5 ma v ds = C 15 v, v gs = ? v dynamic electrical characteristics common source g fs 1 3.5 1.5 6 ms v ds = C 15 v, v gs = ? v forward transconductance common source output conductance g os 20 20 s v ds = C 15 v, v gs = ? v common source input capacitance c iss 25 25 pf v ds = C 15 v, v gs = ? v f = 1 mhz common source c rss 77pfv ds = C 15 v, v gs = ? v f = 1 mhz reverse transfer capacitance 1000 n. shiloh road, garland, tx 75042 (972) 487-1287 fax (972) 276-3375 www.interfet.com databook.fxp 1/13/99 2:09 pm page b-18
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